Agent skill · NVIDIA
hsb-ip-create-top
Create or explain fixed-format HSB FPGA_top.sv wrappers from validated HOLOLINK_def.svh files. Do not use for def generation or validation.
What it needs
About 6k tokens when loaded.
What this skill does
HSB IP Create Top Skill Purpose Create a fixed-format SystemVerilog top-level scaffold that instantiates HOLOLINKtop and declares the HSB-facing signals required by a validated HOLOLINKdef.svh. This skill owns only the top-level scaffold around the HSB IP: SPDX/Apache license header HOLOLINKdef.svh include FPGAtop module shell HSB-facing signal declarations HOLOLINKtop instantiation comments/TODOs for top-level integration Use hsb-ip-def for HOLOLINKdef.svh generation and validation. Do not create or validate the defs file here. Prerequisites A validated HOLOLINKdef.svh path or pasted file content is required before generating FPGAtop.sv. Live HOLOLINKtop.sv source is preferred when source-sensitive port extraction is needed; bundled references cover known rev 16'h2604 and compatible rev 16'h2603. The user must provide or accept the output path when writing a scaffold file. Instructions Require a validated HOLOLINKdef.svh before creating FPGAtop.sv. If the user does not have one, invoke or direct them to hsb-ip-def first. Treat live HOLOLINKtop.sv as the source of truth for ports, directions, macro gates, and IP revision whenever it is available. First classify the request as Standalone Create Top, Def-Skill Handoff, or Explain. Load only the references required for that workflow and do not re-read the same reference just to reconfirm formatting. Use references/fixed-format.md as the baked formatting and naming style. Do not inspect example top-level files just to confirm formatting during normal generation. Emit a fixed-format scaffold, not a complete project top. Because the surrounding design is unknown, the generated FPGAtop module normally has no top-level ports. Derive active signal groups from the validated defs file. Do not connect ports that are absent from HOLOLINKtop under the active macro set. Preserve HOLOLINKtop port shapes exactly: keep packed vector widths before the signal name and unpacked interface-array dimensions after the signal name. …
How to use it
Reference it in AdaL, Claude Code, Cursor or any coding agent — nothing to install:
@skills NVIDIA/hsb-ip-create-top